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Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor., , , , , , , , , и 2 other автор(ы). IEEE J. Solid State Circuits, 46 (1): 184-193 (2011)A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm., , , , , , и . VLSI Design, стр. 252-257. IEEE Computer Society, (2010)A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores., , , , и . VLSI Design, стр. 273-278. IEEE Computer Society, (2008)An IA-32 processor with a wide voltage operating range in 32nm CMOS., , , , , , , , , и 9 other автор(ы). Hot Chips Symposium, стр. 1-37. IEEE, (2012)F3: Adaptive design techniques for energy efficiency., , , , , и . ISSCC, стр. 514-515. IEEE, (2014)A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip., , , , , , , , и . VLSI Design, стр. 292-297. IEEE Computer Society, (2012)A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS., , , и . VLSI Design, стр. 301-306. IEEE Computer Society, (2009)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 174-175. IEEE, (2010)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS., , , , , , , , , и 11 other автор(ы). ISSCC, стр. 66-68. IEEE, (2012)5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS., , , , , , , , , и 12 other автор(ы). IEEE J. Solid State Circuits, 37 (11): 1421-1432 (2002)