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Disambiguation of "Aseron, Paolo A."

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Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.

, , , , , , , , , , , and . IEEE J. Solid State Circuits, 46 (1): 184-193 (2011)

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Giordano Paolo

Paolo Molteni

Paolo Bavaj

Paolo Fornara

Paolo Imperia

 

Other publications of authors with the same name

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops., , , , , , , , , and 1 other author(s). IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (3): 208-217 (2011)4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging., , , , , , and . ISSCC, page 1-3. IEEE, (2015)An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS., , , , , , , , , and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)An IA-32 processor with a wide voltage operating range in 32nm CMOS., , , , , , , , , and 9 other author(s). Hot Chips Symposium, page 1-37. IEEE, (2012)2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process., , , , , , , , , and 1 other author(s). ISSCC, page 274-275. IEEE, (2008)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS., , , , , , , , , and 11 other author(s). ISSCC, page 66-68. IEEE, (2012)A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 52 (4): 961-971 (2017)All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control., , , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (9): 2017-2025 (2011)A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 46 (1): 194-208 (2011)