Author of the publication

Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design.

, , and . DAC, page 533-538. IEEE, (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design., , and . DAC, page 533-538. IEEE, (2007)Supply Voltage Noise Aware ATPG for Transition Delay Faults., , and . VTS, page 179-186. IEEE Computer Society, (2007)A novel framework for faster-than-at-speed delay test considering IR-drop effects., , and . ICCAD, page 198-203. ACM, (2006)Timing-based delay test for screening small delay defects., , and . DAC, page 320-325. ACM, (2006)A Cognitive Brain-Computer Interface for Patients with Amyotrophic Lateral Sclerosis., , , , , , , , , and . SMC, page 3187-3191. IEEE, (2015)Frequency peak features for low-channel classification in motor imagery paradigms., , and . NER, page 321-324. IEEE, (2017)A machine learning approach to taking EEG-based brain-computer interfaces out of the lab.. University of Tübingen, Germany, (2018)Brain-computer interfacing in amyotrophic lateral sclerosis: Implications of a resting-state EEG analysis., , , , , , , , , and . EMBC, page 6979-6982. IEEE, (2015)Interpretable Riemannian Classification in Brain-Computer Interfacing., , and . GBCIC, Verlag der Technischen Universitaet Graz, (2019)MOABB: Trustworthy algorithm benchmarking for BCIs., and . CoRR, (2018)