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A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links.

, , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (12): 1387-1391 (2017)

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Integrating bio-sensing functions on CMOS chips., , , , , , and . APCCAS, page 548-551. IEEE, (2010)Robust and fault-tolerant circuit design for nanometer-scale devices and single-electron transistors., and . ISCAS (3), page 685-688. IEEE, (2004)Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage., and . ISCAS, page 1871-1874. IEEE, (2007)Load Optimization of an Inductive Power Link for Remote Powering of Biomedical Implants., , , , , , and . ISCAS, page 533-536. IEEE, (2009)Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity., , and . ISCAS (5), page 453-456. IEEE, (2003)Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 339-351 (2016)Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library., , , , , and . DAC, page 1014-1019. ACM, (2011)Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors., , , and . DAC, page 42-47. ACM, (2012)A low-power, multichannel gated oscillator-based CDR for short-haul applications., , , and . ISLPED, page 107-110. ACM, (2005)Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology., , , and . NORCAS, page 1-4. IEEE, (2015)