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A carbon nanotube transistor based RISC-V processor using pass transistor logic., , , , , и . ISLPED, стр. 1-6. IEEE, (2017)CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics., , , , , , , , , и 2 other автор(ы). DAC, стр. 949-954. IEEE, (2021)A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm., , , , , , , , , и 8 other автор(ы). VLSI Circuits, стр. 150-. IEEE, (2019)MeNDA: a near-memory multi-way merge solution for sparse transposition and dataflows., , , , , , , и . ISCA, стр. 245-258. ACM, (2022)A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET., , , , , , , , , и 2 other автор(ы). VLSI Technology and Circuits, стр. 202-203. IEEE, (2022)Squaring the circle: Executing Sparse Matrix Computations on FlexTPU - A TPU-Like Processor., , , , , , и . PACT, стр. 148-159. ACM, (2022)SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator., , , , , и . MICRO, стр. 1005-1021. ACM, (2021)HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework., , , , , , , и . IISWC, стр. 13-24. IEEE, (2020)Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective., , , и . ISPASS, стр. 202-211. IEEE, (2019)Sparse-TPU: adapting systolic arrays for sparse matrices., , , , , , , , , и . ICS, стр. 19:1-19:12. ACM, (2020)