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Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations., , , , , , and . J. Low Power Electron., 8 (1): 113-124 (2012)A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows., , , , , and . DATE, page 220-225. IEEE, (2022)Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities., , , , , , and . PATMOS, volume 5953 of Lecture Notes in Computer Science, page 266-275. Springer, (2009)Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications., , , , , , , and . VLSI Technology and Circuits, page 216-217. IEEE, (2022)11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint., , , , , , , , , and 3 other author(s). ISSCC, page 210-212. IEEE, (2024)Unified Power Format (UPF) methodology in a vendor independent flow., , , and . PATMOS, page 82-88. IEEE, (2015)Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor., , , , , and . PATMOS, page 111-117. IEEE, (2015)A 2.5μW 0.0067mm2 automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V VDD range., , , and . ISSCC, page 304-306. IEEE, (2018)Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges., , , , , , and . ICECS, page 157-160. IEEE, (2018)Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction., , , and . ASYNC, page 48-57. IEEE Computer Society, (2008)