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Optimization of DRAM based PIM Architecture for Energy-Efficient Deep Neural Network Training.

, , , and . ISCAS, page 1472-1476. IEEE, (2022)

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Channel Models for Physical Unclonable Functions based on DRAM Retention Measurements., , , , , , and . REDUNDANCY, page 149-154. IEEE, (2019)Efficient Generation of Application Specific Memory Controllers., , , , , , , , and . MEMSYS, page 233-247. ACM, (2020)Efficient coding scheme for DDR4 memory subsystems., , , , , , and . MEMSYS, page 148-157. ACM, (2018)Addressing the Combined Effect of Transistor and Interconnect Aging in SRAM towards Silicon Lifecycle Management., , , , , , , , and . VTS, page 1-5. IEEE, (2024)Optimization of DRAM based PIM Architecture for Energy-Efficient Deep Neural Network Training., , , and . ISCAS, page 1472-1476. IEEE, (2022)A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs., , , , , , , and . ASP-DAC, page 35-42. ACM, (2021)Fast validation of DRAM protocols with timed petri nets., , , , , and . MEMSYS, page 133-147. ACM, (2019)A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing., , , , , and . SAMOS, volume 11733 of Lecture Notes in Computer Science, page 429-441. Springer, (2019)An In-DRAM Neural Network Processing Engine., , , , , , and . ISCAS, page 1-5. IEEE, (2019)Improving the error behavior of DRAM by exploiting its Z-channel property., , , , , and . DATE, page 1492-1495. IEEE, (2018)