( en | de | ru )

 

Disambiguation of "Ienne, Paolo"

Author of the publication

copydeleteadd this publication to your clipboard
High performance comparison-based sorting algorithm on many-core GPUs.

, , , , and . IPDPS, page 1-10. IEEE, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Giordano Paolo

Paolo Molteni

Paolo Bavaj

Paolo Fornara

Paolo Imperia

 

Other publications of authors with the same name

A first step towards automatic application of power analysis countermeasures., , , , and . DAC, page 230-235. ACM, (2011)Speculative DMA for architecturally visible storage in instruction set extensions., , , and . CODES+ISSS, page 243-248. ACM, (2008)Way Stealing: cache-assisted automatic instruction set extensions., , , and . DAC, page 31-36. ACM, (2009)Virtual memory window for application-specific reconfigurable coprocessors., , and . DAC, page 948-953. ACM, (2004)Digital Connectionist Hardware: Current Problems and Future Challenges.. IWANN, volume 1240 of Lecture Notes in Computer Science, page 688-713. Springer, (1997)A flexible DSP block to enhance FPGA arithmetic performance., , , , , and . FPT, page 70-77. IEEE Computer Society, (2009)On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations., , , and . IEEE Des. Test Comput., 21 (6): 524-535 (2004)Providing QoS to connection-less packet-switched NoC by implementing DiffServ functionalities., , , and . SoC, page 37-40. IEEE, (2004)Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence., and . FPL, page 225-233. IEEE, (2021)A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions., , , , , , , and . CHES, volume 5747 of Lecture Notes in Computer Science, page 205-219. Springer, (2009)