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Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET., , , , , , , , , and 2 other author(s). ESSCIRC, page 183-186. IEEE, (2017)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)Design space exploration for field programmable compressor trees., , , , , , and . CASES, page 207-216. ACM, (2008)3D serial TSV link for low-power chip-to-chip communication., , , and . ICICDT, page 1-4. IEEE, (2014)10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 266-268. IEEE, (2018)A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET., , , , , , , , , and 1 other author(s). ISSCC, page 112-114. IEEE, (2019)Fast and accurate BER estimation methodology for I/O links based on extreme value theory., , , , , , and . DATE, page 503-508. EDA Consortium San Jose, CA, USA / ACM DL, (2013)3D configuration caching for 2D FPGAs., , , , , , and . FPGA, page 286. ACM, (2009)DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology., , , , , , , , , and 1 other author(s). ESSCIRC, page 115-118. IEEE, (2017)