Author of the publication

Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs.

, , , , , and . IEEE Trans. Emerg. Top. Comput., 5 (3): 340-352 (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures., , , and . ACM Great Lakes Symposium on VLSI, page 147-152. ACM, (2018)Enhancing Hardware Security with Emerging Transistor Technologies., , , , , and . ACM Great Lakes Symposium on VLSI, page 305-310. ACM, (2016)Cyclic Obfuscation for Creating SAT-Unresolvable Circuits., , , , , and . ACM Great Lakes Symposium on VLSI, page 173-178. ACM, (2017)On the Impossibility of Approximation-Resilient Circuit Locking., , and . HOST, page 161-170. IEEE, (2019)A Security Analysis of Circuit Clock Obfuscation., , , and . Cryptogr., 6 (3): 43 (2022)Emerging Technology-Based Design of Primitives for Hardware Security., , , , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 13 (1): 3:1-3:19 (2016)Enhancing Solver-based Generic Side-Channel Analysis with Machine Learning., and . ACM Great Lakes Symposium on VLSI, page 345-350. ACM, (2023)IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits., , and . ICCAD, page 1-7. ACM, (2019)Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs., , , , , and . IEEE Trans. Emerg. Top. Comput., 5 (3): 340-352 (2017)Circuit Deobfuscation from Power Side-Channels using Pseudo-Boolean SAT., and . ICCAD, page 1-9. IEEE, (2021)