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Behavioural Scheduling to Balance the Bit-Level Computational Effort., , , and . ISVLSI, page 99-104. IEEE Computer Society, (2004)Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis., , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 617-627. Springer, (2003)Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits., , , and . DSD, page 464-471. IEEE Computer Society, (2008)Arrival time aware scheduling to minimize clock cycle length., , , and . ASP-DAC, page 1018-1021. ACM Press, (2005)Pre-synthesis optimization of multiplications to improve circuit performance., , , and . DATE, page 1306-1311. European Design and Automation Association, Leuven, Belgium, (2006)Exploiting Bit-Level Delay Calculations to Soften Read-After-Write Dependences in Behavioral Synthesis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (9): 1589-1601 (2007)Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis., , , and . DATE, page 1252-1257. IEEE Computer Society, (2005)Area optimization of multi-cycle operators in high-level synthesis., , , and . DATE, page 449-454. EDA Consortium, San Jose, CA, USA, (2007)Behavioural Bitwise Scheduling Based on Computational Effort Balancing., , , and . DATE, page 684-685. IEEE Computer Society, (2004)Performance-driven read-after-write dependencies softening in high-level synthesis., , , and . ICCAD, page 7-12. IEEE Computer Society, (2005)