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Disambiguation of "Molina, María C."

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Arrival time aware scheduling to minimize clock cycle length.

, , , and . ASP-DAC, page 1018-1021. ACM Press, (2005)

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María Isabel Grasa Molina

Jose Maria Gonzalez Molina

Maria C Schmitt

Maria C Schmitt

Carlos Molina

 

Other publications of authors with the same name

High-level synthesis of multiple-precision circuitsindependent of data-objects length., , and . DAC, page 612-615. ACM, (2002)A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths., , , , and . Integr., 46 (2): 119-130 (2013)High-Level Allocation to Minimize Internal Hardware Wastage., , and . DATE, page 10264-10269. IEEE Computer Society, (2003)Applying speculation techniques to implement functional units., , , , , and . ICCD, page 74-80. IEEE Computer Society, (2008)Behavioural Scheduling to Balance the Bit-Level Computational Effort., , , and . ISVLSI, page 99-104. IEEE Computer Society, (2004)Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis., , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 617-627. Springer, (2003)Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis., , , , and . DSD, page 267-273. IEEE Computer Society, (2008)Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis., , , and . DSD, page 308-315. IEEE Computer Society, (2002)Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis., , , and . DATE, page 1252-1257. IEEE Computer Society, (2005)Area optimization of multi-cycle operators in high-level synthesis., , , and . DATE, page 449-454. EDA Consortium, San Jose, CA, USA, (2007)