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AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs.

S. Tang, S. Yin, S. Zheng, P. Ouyang, F. Tu, L. Yao, J. Wu, W. Cheng, L. Liu, and S. Wei. NVMSA, page 1-6. IEEE, (2017)

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Shiwei Tu

Nguyen Tu

Wei Tu

Changfeng Tu

Chunling Tu

Other publications of authors with the same name

MoNA: Mobile Neural Architecture with Reconfigurable Parallel Dimensions.W. Wu, S. Yin, F. Tu, L. Liu, and S. Wei. NEWCAS, page 1-4. IEEE, (2019)A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications.S. Yin, P. Ouyang, S. Tang, F. Tu, X. Li, S. Zheng, T. Lu, J. Gu, L. Liu, and S. Wei. IEEE J. Solid State Circuits, 53 (4): 968-982 (2018)RNA: a reconfigurable architecture for hardware neural acceleration.F. Tu, S. Yin, P. Ouyang, L. Liu, and S. Wei. DATE, page 695-700. ACM, (2015)STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction.F. Xiong, F. Tu, M. Shi, Y. Wang, L. Liu, S. Wei, and S. Yin. DAC, page 1-6. IEEE, (2020)INSPIRE: in-storage private information retrieval via protocol and architecture co-design.J. Lin, L. Liang, Z. Qu, I. Ahmad, L. Liu, F. Tu, T. Gupta, Y. Ding, and Y. Xie. ISCA, page 102-115. ACM, (2022)ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving In DNN Training.X. Lin, L. Sun, F. Tu, L. Liu, X. Li, S. Wei, and S. Yin. DAC, page 751-756. IEEE, (2021)ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration.F. Tu, Y. Wang, Z. Wu, L. Liang, Y. Ding, B. Kim, L. Liu, S. Wei, Y. Xie, and S. Yin. IEEE J. Solid State Circuits, 58 (1): 243-255 (2023)Towards Efficient Compact Network Training on Edge-Devices.F. Xiong, F. Tu, S. Yin, and S. Wei. ISVLSI, page 61-67. IEEE, (2019)SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration.F. Tu, Y. Wang, L. Liang, Y. Ding, L. Liu, S. Wei, S. Yin, and Y. Xie. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (1): 109-121 (2023)Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane.J. Deng, X. Tang, J. Zhang, Y. Li, L. Zhang, B. Han, H. He, F. Tu, L. Liu, S. Wei and 2 other author(s). MICRO, page 1395-1408. ACM, (2023)

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Disambiguation of "Tu, Fengbin"

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AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs.

Please choose a person to relate this publication to

Shiwei Tu

Nguyen Tu

Wei Tu

Changfeng Tu

Chunling Tu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tu, Fengbin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs.

Please choose a person to relate this publication to

Shiwei Tu

Nguyen Tu

Wei Tu

Changfeng Tu

Chunling Tu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs.