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Другие публикации лиц с тем же именем

In-Hardware Moving Compute to Data Model to Accelerate Thread Synchronization on Large Multicores., , , и . IEEE Micro, 40 (1): 83-92 (2020)POSTER: Exploiting Multi-Level Task Dependencies to Prune Redundant Work in Relax-Ordered Task-Parallel Algorithms., , , и . PACT, стр. 495-496. IEEE, (2019)A framework to accelerate sequential programs on homogeneous multicores., , , и . VLSI-SoC, стр. 344-347. IEEE, (2013)CoDG-ReRAM: An Algorithm-Hardware Co-design to Accelerate Semi-Structured GNNs on ReRAM., , , , , , , , , и 1 other автор(ы). ICCD, стр. 280-289. IEEE, (2022)Characterization of mitigation schemes against timing-based side-channel attacks on PCIe hardware., , и . ISQED, стр. 1-6. IEEE, (2022)Seeds of SEED: Characterizing Enclave-level Parallelism in Secure Multicore Processors., и . SEED, стр. 203-209. IEEE, (2021)ConNOC: A Practical Timing Channel Attack on Network-on-chip Hardware in a Multicore Processor., и . HOST, стр. 192-202. IEEE, (2021)Timing-based side-channel attack and mitigation on PCIe connected distributed embedded systems., , и . HPEC, стр. 1-7. IEEE, (2021)Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems., , , , , и . RTSS, стр. 305-316. IEEE Computer Society, (2011)A model to exploit power-performance efficiency in superscalar processors via structure resizing., и . ACM Great Lakes Symposium on VLSI, стр. 215-220. ACM, (2010)