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Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node.

Y. Xiong, A. Feeley, L. Massengill, B. Bhuva, S. Wen, and R. Fung. IRPS, page 1-5. IEEE, (2021)

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Wen-Jie Dai

Zhou Jie

Yucheng Jie

Jie Ding

Jie Huang

Other publications of authors with the same name

A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning.S. Kundu, M. Liu, R. Wong, S. Wen, and C. Kim. ISSCC, page 308-310. IEEE, (2018)Correlation of Heavy-Ion and Laser Testing on a DC/DC PWM Controller.Y. Ren, S. Shi, L. Chen, H. Wang, L. Gao, G. Guo, S. Wen, R. Wong, and N. van Vonno. J. Electron. Test., 29 (4): 609-616 (2013)Single-Event Transient Measurements on a DC/DC Pulse Width Modulator Using Heavy Ion, Proton, and Pulsed Laser.Y. Ren, A. He, S. Shi, G. Guo, L. Chen, S. Wen, R. Wong, N. van Vonno, and B. Bhuva. J. Electron. Test., 30 (1): 149-154 (2014)Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies.J. Cao, L. Xu, B. Bhuva, S. Wen, R. Wong, B. Narasimham, and L. Massengill. IRPS, page 1-5. IEEE, (2019)Thermal Neutron Induced Soft Errors in 7-nm Bulk FinFET Node.L. Xu, J. Cao, J. Brockman, C. Cazzaniga, C. Frost, S. Wen, R. Fung, and B. Bhuva. IRPS, page 1-5. IEEE, (2020)Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.N. Jing, J. Lee, Z. Feng, W. He, Z. Mao, S. Wen, R. Wong, and L. He. FPL, page 282-285. IEEE Computer Society, (2011)IZIP: In-place zero overhead interconnect protection via PIP redundancy.Y. Luo, A. Evans, S. Wen, R. Wong, and G. Chen. ASICON, page 565-568. IEEE, (2017)Placement of repair circuits for in-field FPGA repair.M. Wirthlin, J. Jensen, A. Wilson, W. Howes, S. Wen, and R. Wong. FPGA, page 115-124. ACM, (2013)Soft Error Characterization of D-FFs at the 5-nm Bulk FinFET Technology for the Terrestrial Environment.Y. Xiong, A. Feeley, N. Pieper, D. Ball, B. Narasimham, J. Brockman, N. Dodds, S. Wender, S. Wen, R. Fung and 1 other author(s). IRPS, page 7. IEEE, (2022)Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS.D. Rennie, D. Li, M. Sachdev, B. Bhuva, S. Jagannathan, S. Wen, and R. Wong. CICC, page 1-4. IEEE, (2011)

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Disambiguation of "Wen, Shi-Jie"

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Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node.

Please choose a person to relate this publication to

Wen-Jie Dai

Zhou Jie

Yucheng Jie

Jie Ding

Jie Huang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wen, Shi-Jie"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node.

Please choose a person to relate this publication to

Wen-Jie Dai

Zhou Jie

Yucheng Jie

Jie Ding

Jie Huang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node.