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Disambiguation of "Nannarelli, Alberto"

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FPGA realization of RNS to binary signed conversion architecture.

, , , and . ISCAS (4), page 350-353. IEEE, (2001)

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Alberto Moreira

Alberto Coda

Alberto Fierro

Alberto Ricco

Alberto Moreira

 

Other publications of authors with the same name

Power characterization of digital filters implemented on FPGA., , , and . ISCAS (5), page 801-804. IEEE, (2002)Twenty years of research on RNS for DSP: Lessons learned and future perspectives., , , and . ISIC, page 436-439. IEEE, (2014)Design of power efficient FPGA based hardware accelerators for financial applications., , and . NORCHIP, page 1-4. IEEE, (2012)On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters., , and . VLSI-SoC (Selected Papers), volume 313 of IFIP Advances in Information and Communication Technology, page 174-190. Springer, (2008)Guest Editorial: Special Section on Emerging and Impacting Trends on Computer Arithmetic., , , and . IEEE Trans. Emerg. Top. Comput., 10 (3): 1239-1240 (2022)Unified Digit Selection for Radix-4 Recurrence Division and Square Root., , , , , and . IEEE Trans. Computers, 73 (1): 292-300 (January 2024)FPGA Based Acceleration of Decimal Operations.. ReConFig, page 146-151. IEEE Computer Society, (2011)Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16., and . IEEE Symposium on Computer Arithmetic, page 60-. IEEE Computer Society, (1999)FPGA implementation of decimal processors for hardware acceleration., , and . NORCHIP, page 1-4. IEEE, (2011)Power efficient design of parallel/serial FIR filters in RNS., , , , and . ACSCC, page 1015-1019. IEEE, (2012)