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Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers.

A. Okazaki, P. Narayanan, S. Ambrogio, K. Hosokawa, H. Tsai, A. Nomura, T. Yasuda, C. Mackin, A. Friz, M. Ishii, Y. Kohda, K. Spoon, A. Chen, A. Fasoli, M. Rasch, and G. Burr. ISCAS, page 3319-3323. IEEE, (2022)

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Pritish Sinha

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Other publications of authors with the same name

Parameter variation sensing and estimation in nanoscale fabrics.J. Zhang, M. Rahman, P. Narayanan, S. Khasanvis, and C. Moritz. J. Parallel Distributed Comput., 74 (6): 2504-2511 (2014)Overview of the IBM Neural Computer Architecture.P. Narayanan, C. Cox, A. Asseman, N. Antoine, H. Huels, W. Wilcke, and A. Ozcan. CoRR, (2020)CMOS Control Enabled Single-Type FET NASIC.P. Narayanan, M. Leuchtenburg, T. Wang, and C. Moritz. ISVLSI, page 191-196. IEEE Computer Society, (2008)Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges.C. Mackin, P. Narayanan, S. Ambrogio, H. Tsai, K. Spoon, A. Fasoli, A. Chen, A. Friz, R. Shelby, and G. Burr. IRPS, page 1-10. IEEE, (2020)Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics.P. Vijayakumar, P. Narayanan, I. Koren, C. Krishna, and C. Moritz. NANOARCH, page 181-188. IEEE Computer Society, (2011)Validating cascading of crossbar circuits with an integrated device-circuit exploration.P. Narayanan, C. Moritz, K. won Park, and C. Chui. NANOARCH, page 37-42. IEEE Computer Society, (2009)Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited).M. Frank, N. Li, M. Rasch, S. Jain, C. Chen, R. Muralidhar, J. Han, V. Narayanan, T. Philip, K. Brew and 11 other author(s). IRPS, page 1-10. IEEE, (2023)Deep Learning with Limited Numerical Precision.S. Gupta, A. Agrawal, K. Gopalakrishnan, and P. Narayanan. ICML, volume 37 of JMLR Workshop and Conference Proceedings, page 1737-1746. JMLR.org, (2015)Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited).K. Hosokawa, P. Narayanan, S. Ambrogio, H. Tsai, C. Mackin, A. Fasoli, A. Friz, A. Chen, J. Luquin, K. Spoon and 2 other author(s). ISCAS, page 1-5. IEEE, (2021)Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers.A. Okazaki, P. Narayanan, S. Ambrogio, K. Hosokawa, H. Tsai, A. Nomura, T. Yasuda, C. Mackin, A. Friz, M. Ishii and 6 other author(s). ISCAS, page 3319-3323. IEEE, (2022)

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Disambiguation of "Narayanan, Pritish"

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Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers.

Please choose a person to relate this publication to

Pritish Sinha

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Narayanan, Pritish"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers.

Please choose a person to relate this publication to

Pritish Sinha

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers.