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Disambiguation of "Narayanan, Vijay"

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Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited).

, , , , , , , , , , , , , , , , , , , , and . IRPS, page 1-10. IEEE, (2023)

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Vijay Narayanan Swaminathan

Balakumar Vijayakrishnan

Vijay Divi

Vijay Singh

P Narayanan

 

Other publications of authors with the same name

Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators., , , , , , , , , and 3 other author(s). CoRR, (2023)3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis., , , , and . ICCD, page 254-259. IEEE Computer Society, (2009)Interface engineering of Si1-xGex gate stacks for high performance dual channel CMOS., , , , , , , , , and 1 other author(s). ASICON, page 573-576. IEEE, (2017)PBTI in InGaAs MOS capacitors with Al2O3/HfO2/TiN gate stacks: Interface-state generation., , , , and . IRPS, page 5. IEEE, (2018)In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit Memory., , , , , , , , , and 8 other author(s). CoRR, (2022)Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited)., , , , , , , , , and 11 other author(s). IRPS, page 1-10. IEEE, (2023)Gradient descent-based programming of analog in-memory computing cores., , , , , , , , , and 4 other author(s). CoRR, (2023)Characterizing the soft error vulnerability of multicores running multithreaded applications., , and . SIGMETRICS, page 379-380. ACM, (2010)Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited)., , , , , , , , , and 15 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing., , , , , , , , , and 14 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)