( en | de | ru )

 

Disambiguation of "Collini, Luca"

Author of the publication

copydeleteadd this publication to your clipboard
Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design.

, , , , , , , , , , , and . ICCAD, page 157:1-157:9. ACM, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Luca Rizzini

Luca Tranchini

Luca Tuninetti

Alfonz Luca

Luca Criscuolo

 

Other publications of authors with the same name

Reconfigurable Logic for Hardware IP Protection: Opportunities and Challenges., , , and . ICCAD, page 131:1-131:7. ACM, (2022)C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap?, , and . CoRR, (2024)ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning., , , , , , , and . DAC, page 1-6. IEEE, (2023)A Composable Design Space Exploration Framework to Optimize Behavioral Locking., , and . DATE, page 1359-1364. IEEE, (2022)ConVERTS: Contrastively Learning Structurally InVariant Netlist Representations., , , , , and . MLCAD, page 1-6. IEEE, (2023)Designing ML-resilient locking at register-transfer level., , , , , and . DAC, page 769-774. ACM, (2022)Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design., , , , , , , , , and 2 other author(s). ICCAD, page 157:1-157:9. ACM, (2022)On the Optimization of Behavioral Logic Locking for High-Level Synthesis., , , , , and . CoRR, (2021)ALICE: an automatic design flow for eFPGA redaction., , , , , , , , and . DAC, page 781-786. ACM, (2022)Oscillations of a rocking block with an added pendulum., , , , and . J. Syst. Control. Eng., 230 (2): 104-114 (2016)