( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning.

, , , , , , , и . DAC, стр. 1-6. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Luca Rizzini

Luca Tranchini

Luca Tuninetti

Alfonz Luca

Marcello Lucà

 

Другие публикации лиц с тем же именем

Reconfigurable Logic for Hardware IP Protection: Opportunities and Challenges., , , и . ICCAD, стр. 131:1-131:7. ACM, (2022)ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning., , , , , , , и . DAC, стр. 1-6. IEEE, (2023)Oscillations of a rocking block with an added pendulum., , , , и . J. Syst. Control. Eng., 230 (2): 104-114 (2016)On the Optimization of Behavioral Logic Locking for High-Level Synthesis., , , , , и . CoRR, (2021)ALICE: an automatic design flow for eFPGA redaction., , , , , , , , и . DAC, стр. 781-786. ACM, (2022)Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design., , , , , , , , , и 2 other автор(ы). ICCAD, стр. 157:1-157:9. ACM, (2022)A Composable Design Space Exploration Framework to Optimize Behavioral Locking., , и . DATE, стр. 1359-1364. IEEE, (2022)ConVERTS: Contrastively Learning Structurally InVariant Netlist Representations., , , , , и . MLCAD, стр. 1-6. IEEE, (2023)Designing ML-resilient locking at register-transfer level., , , , , и . DAC, стр. 769-774. ACM, (2022)