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A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.

, , , , , , , , , , , , , , , , , and . ESSCIRC, page 269-272. IEEE, (2022)

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Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study., , and . ACM Great Lakes Symposium on VLSI, page 163-168. ACM, (2011)High-level synthesis of accelerators in embedded scalable platforms., , and . ASP-DAC, page 204-211. IEEE, (2016)Opinion: Why science needs philosophy, , , , , , , , and . Proceedings of the National Academy of Sciences, 116 (10): 3948--3952 (2019)Accelerators and Coherence: An SoC Perspective., , and . IEEE Micro, 38 (6): 36-45 (2018)On the design of scalable and reusable accelerators for big data applications., , , , and . Conf. Computing Frontiers, page 406-411. ACM, (2016)Agile SoC Development with Open ESP : Invited Paper., , , , , , , , and . ICCAD, page 96:1-96:9. IEEE, (2020)A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components., , , , , , , , , and 8 other author(s). ICCAD, page 20:1-20:9. ACM, (2022)Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip., , , , and . CASES, page 3:1-3:10. ACM, (2016)An Analysis of Accelerator Coupling in Heterogeneous Architectures., , , and . DAC, page 202:1-202:6. ACM, (2015)ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning., , , , and . DATE, page 1049-1054. IEEE, (2020)