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A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.

T. Jia, P. Mantovani, M. dos Santos, D. Giri, J. Zuckerman, E. Loscalzo, M. Cochet, K. Swaminathan, G. Tombesi, J. Zhang, N. Chandramoorthy, J. Wellman, K. Tien, L. Carloni, K. Shepard, D. Brooks, G. Wei, and P. Bose. ESSCIRC, page 269-272. IEEE, (2022)

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Gabriele Graefen

Der wissenschaftliche Artikel: Textart und TextorganisationG. Graefen. Uni Dortmund, (1996)

Gabriele Kast

Gabriele Isensee

Gabriele Bülow

Gabriele Wiesenthal

Other publications of authors with the same name

A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.M. dos Santos, T. Jia, M. Cochet, K. Swaminathan, J. Zuckerman, P. Mantovani, D. Giri, J. Zhang, E. Loscalzo, G. Tombesi and 8 other author(s). ICCAD, page 20:1-20:9. ACM, (2022)DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.F. Gao, T. Chang, A. Li, M. Orenes-Vera, D. Giri, P. Jackson, A. Ning, G. Tziantzioulis, J. Zuckerman, J. Tu and 7 other author(s). CICC, page 1-2. IEEE, (2023)14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.M. dos Santos, T. Jia, J. Zuckerman, M. Cochet, D. Giri, E. Loscalzo, K. Swaminathan, T. Tambe, J. Zhang, A. Buyuktosunoglu and 19 other author(s). ISSCC, page 262-264. IEEE, (2024)A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.T. Jia, P. Mantovani, M. dos Santos, D. Giri, J. Zuckerman, E. Loscalzo, M. Cochet, K. Swaminathan, G. Tombesi, J. Zhang and 8 other author(s). ESSCIRC, page 269-272. IEEE, (2022)Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures.J. Zuckerman, J. Wellman, A. Vanamali, M. Shankar, G. Tombesi, K. Swaminathan, K. Lee, M. Kapur, R. Philhower, P. Bose and 1 other author(s). CoRR, (2024)

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Disambiguation of "Tombesi, Gabriele"

Please choose a person to relate this publication to

Gabriele Graefen

Gabriele Kast

Gabriele Isensee

Gabriele Bülow

Gabriele Wiesenthal

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tombesi, Gabriele"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.

Please choose a person to relate this publication to

Gabriele Graefen

Gabriele Kast

Gabriele Isensee

Gabriele Bülow

Gabriele Wiesenthal

Other publications of authors with the same name

Disambiguation