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A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.

T. Jia, P. Mantovani, M. dos Santos, D. Giri, J. Zuckerman, E. Loscalzo, M. Cochet, K. Swaminathan, G. Tombesi, J. Zhang, N. Chandramoorthy, J. Wellman, K. Tien, L. Carloni, K. Shepard, D. Brooks, G. Wei, and P. Bose. ESSCIRC, page 269-272. IEEE, (2022)

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Sushmitha Swaminathan

Karthik Arumugam

Ashwin Swaminathan

Karthik Gururaj

Karthik Narasimhan

Other publications of authors with the same name

Enabling architectural innovations using non-volatile memory.V. Narayanan, V. Saripalli, K. Swaminathan, R. Mukundrajan, G. Sun, Y. Xie, and S. Datta. ACM Great Lakes Symposium on VLSI, page 439-444. ACM, (2011)Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores.E. Kultursay, K. Swaminathan, V. Saripalli, V. Narayanan, M. Kandemir, and S. Datta. CODES+ISSS, page 245-254. ACM, (2012)Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures.K. Swaminathan, J. Kotra, H. Liu, J. Sampson, M. Kandemir, and V. Narayanan. VLSID, page 221-226. IEEE Computer Society, (2015)Energy Efficiency Boost in the AI-Infused POWER10 Processor.B. Thompto, D. Nguyen, J. Moreira, R. Bertran, H. Jacobson, R. Eickemeyer, R. Rao, M. Goulet, M. Byers, C. Gonzalez and 16 other author(s). ISCA, page 29-42. IEEE, (2021)An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs.K. Swaminathan, H. Liu, J. Sampson, and V. Narayanan. ISCA, page 241-252. IEEE Computer Society, (2014)14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.M. dos Santos, T. Jia, J. Zuckerman, M. Cochet, D. Giri, E. Loscalzo, K. Swaminathan, T. Tambe, J. Zhang, A. Buyuktosunoglu and 19 other author(s). ISSCC, page 262-264. IEEE, (2024)Dramaton: A Near-DRAM Accelerator for Large Number Theoretic Transforms.Y. Park, S. Pal, A. Amarnath, K. Swaminathan, W. Lu, A. Buyuktosunoglu, and P. Bose. IEEE Comput. Archit. Lett., 23 (1): 108-111 (January 2024)MBET: Resilience Improvement Method for DNNs.A. Buldu, A. Sen, K. Swaminathan, and B. Kahne. AITest, page 72-78. IEEE, (2022)A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.M. dos Santos, T. Jia, M. Cochet, K. Swaminathan, J. Zuckerman, P. Mantovani, D. Giri, J. Zhang, E. Loscalzo, G. Tombesi and 8 other author(s). ICCAD, page 20:1-20:9. ACM, (2022)BRAVO: Balanced Reliability-Aware Voltage Optimization.K. Swaminathan, N. Chandramoorthy, C. Cher, R. Bertran, A. Buyuktosunoglu, and P. Bose. HPCA, page 97-108. IEEE Computer Society, (2017)

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Disambiguation of "Swaminathan, Karthik"

Please choose a person to relate this publication to

Sushmitha Swaminathan

Karthik Arumugam

Ashwin Swaminathan

Karthik Gururaj

Karthik Narasimhan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Swaminathan, Karthik"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.

Please choose a person to relate this publication to

Sushmitha Swaminathan

Karthik Arumugam

Ashwin Swaminathan

Karthik Gururaj

Karthik Narasimhan

Other publications of authors with the same name

Disambiguation