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A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.

, , , , , , , , , , , , , , , , , и . ICCAD, стр. 20:1-20:9. ACM, (2022)

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Shibashish Giri

Wolfgang Girisch

Joseph Girisch

Philipp Girichidis

Jana Girisch

 

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A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components., , , , , , , , , и 8 other автор(ы). ICCAD, стр. 20:1-20:9. ACM, (2022)Agile SoC Development with Open ESP : Invited Paper., , , , , , , , и . ICCAD, стр. 96:1-96:9. IEEE, (2020)DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET., , , , , , , , , и 7 other автор(ы). CICC, стр. 1-2. IEEE, (2023)Accelerators and Coherence: An SoC Perspective., , и . IEEE Micro, 38 (6): 36-45 (2018)The MosaicSim Simulator (Full Technical Report)., , , , , , , , , и . CoRR, (2020)PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs., , , , и . DATE, стр. 1-6. IEEE, (2023)Runtime reconfigurable memory hierarchy in embedded scalable platforms., , и . ASP-DAC, стр. 719-726. ACM, (2019)A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC., , , , , , , , , и 8 other автор(ы). ESSCIRC, стр. 269-272. IEEE, (2022)MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces., , , и . ICCD, стр. 101-108. IEEE, (2021)Work-in-Progress: An Open-Source Platform for Design and Programming of Partially Reconfigurable Heterogeneous SoCs., , , и . CASES, стр. 25-26. IEEE, (2022)