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Disambiguation of "Natarajan, Arun"

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A Highly Integrated Distributed Mixer Receiver for Low-Power Wireless Radios.

, , and . IEEE J. Solid State Circuits, 58 (12): 3421-3432 (December 2023)

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Kasyap Natarajan

Paruthiure Natarajan

Umeswaran Arunagirinathan

Natarajan Thiagarajan

Arupon Natarajan

 

Other publications of authors with the same name

W-band scalable phased arrays for imaging and communications., , , , , and . IEEE Commun. Mag., 53 (4): 196-204 (2015)An Integral Path Self-Calibration Scheme for a Dual-Loop PLL., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (4): 996-1008 (2013)Scalable Spatial Notch Suppression in Spatio-Spectral-Filtering MIMO Receiver Arrays for Digital Beamforming., , and . IEEE J. Solid State Circuits, 51 (12): 3152-3166 (2016)A fully integrated 24-GHz phased-array transmitter in CMOS., , and . IEEE J. Solid State Circuits, 40 (12): 2502-2514 (2005)A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-μm CMOS., , and . IEEE J. Solid State Circuits, 40 (9): 1901-1908 (2005)Introduction to the Special Issue on the 2018 IEEE International Solid-State Circuits Conference (ISSCC)., , , , and . IEEE J. Solid State Circuits, 53 (12): 3343-3346 (2018)A 20 μ W, 0.05mm2 Duty-Cycled Resistor and Frequency-Locked-Loop-based Wheatstone Bridge Interface for Low Resistance Sensing Systems., , , , and . CICC, page 1-2. IEEE, (2021)Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits., , , , , , , , , and 4 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (8): 2243-2252 (2014)6.6 Full-Duplex Receiver with Wideband Multi-Domain FIR Cancellation Based on Stacked-Capacitor, N-Path Switched-Capacitor Delay Lines Achieving >54dB SIC Across 80MHz BW and >15dBm TX Power-Handling., , , , , , , and . ISSCC, page 100-102. IEEE, (2021)9.6 A 1.3mW 0.6V WBAN-compatible sub-sampling PSK receiver in 65nm CMOS., , , and . ISSCC, page 168-169. IEEE, (2014)