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Device Modeling and Circuit Design for Scalable Beyond-CMOS Computing., , , , and . VLSI-SOC, page 210-211. IEEE, (2020)Exploiting Dual-Gate Ambipolar CNFETs for Scalable Machine Learning Classification., , , , , and . CoRR, (2019)Process Variation Model and Analysis for Domain Wall-Magnetic Tunnel Junction Logic., , , , , , and . ISCAS, page 1-5. IEEE, (2020)Transient model with interchangeability for dual-gate ambipolar CNTFET logic design., and . NANOARCH, page 61-66. IEEE, (2017)Sleep stage classification with stochastic Bayesian inference., , , , and . NANOARCH, page 117-122. ACM, (2016)Hybrid Pass Transistor Logic with Dual-Gate Ambipolar CNTFETs., and . CoRR, (2020)Reservoir Computing with Planar Nanomagnet Arrays., , , , , and . CoRR, (2020)Unsupervised Competitive Hardware Learning Rule for Spintronic Clustering Architecture., , , , , , , and . CoRR, (2020)Near-Landauer Reversible Skyrmion Logic with Voltage-Based Propagation., , , , , and . CoRR, (2023)Deep Neuromorphic Networks with Superconducting Single Flux Quanta., , , and . CoRR, (2023)