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A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.

S. Nomura, F. Tachibana, T. Fujita, C. Teh, H. Usui, F. Yamane, Y. Miyamoto, C. Kumtornkittikul, H. Hara, T. Yamashita, J. Tanabe, M. Uchiyama, Y. Tsuboi, T. Miyamori, T. Kitahara, H. Sato, Y. Homma, S. Matsumoto, K. Seki, Y. Watanabe, M. Hamada, and M. Takahashi. ISSCC, page 262-263. IEEE, (2008)

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Fumihiko Sato

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A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit.F. Tachibana, O. Hirabayashi, Y. Takeyama, M. Shizuno, A. Kawasumi, K. Kushida, A. Suzuki, Y. Niki, S. Sasaki, T. Yabe and 1 other author(s). ISSCC, page 320-321. IEEE, (2013)A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems.Y. Tsubouchi, D. Miyashita, Y. Satoh, T. Toi, F. Tachibana, M. Morimoto, J. Wadatsumi, and J. Deguchi. VLSI Circuits, page 149-150. IEEE, (2018)Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision.K. Nakata, A. Maki, D. Miyashita, F. Tachibana, T. Suzuki, and J. Deguchi. ISCAS, page 1. IEEE, (2019)Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction.A. Kawasumi, Y. Takeyama, O. Hirabayashi, K. Kushida, F. Tachibana, Y. Niki, S. Sasaki, and T. Yabe. ICICDT, page 1-4. IEEE, (2012)FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision.A. Maki, D. Miyashita, K. Nakata, F. Tachibana, T. Suzuki, and J. Deguchi. A-SSCC, page 47-50. IEEE, (2018)Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN.K. Nakata, D. Miyashita, A. Maki, F. Tachibana, S. Sasaki, J. Deguchi, and R. Fujimoto. AICAS, page 1-4. IEEE, (2021)A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access.K. Kushida, O. Hirabayashi, F. Tachibana, H. Hara, A. Kawasumi, A. Suzuki, Y. Takeyama, Y. Fujimura, Y. Niki, M. Shizuno and 2 other author(s). A-SSCC, page 161-164. IEEE, (2011)A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.S. Nomura, F. Tachibana, T. Fujita, C. Teh, H. Usui, F. Yamane, Y. Miyamoto, C. Kumtornkittikul, H. Hara, T. Yamashita and 12 other author(s). ISSCC, page 262-263. IEEE, (2008)A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs.A. Kawasumi, Y. Takeyama, O. Hirabayashi, K. Kushida, F. Tachibana, Y. Niki, S. Sasaki, and T. Yabe. VLSIC, page 100-101. IEEE, (2012)A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR.F. Tachibana, H. Ngo, G. Urakawa, T. Toi, M. Ashida, Y. Tsubouchi, M. Nozawa, J. Wadatsumi, H. Kobayashi, and J. Deguchi. ESSCIRC, page 505-508. IEEE, (2022)

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Fumihiko Sato

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