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A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.

S. Nomura, F. Tachibana, T. Fujita, C. Teh, H. Usui, F. Yamane, Y. Miyamoto, C. Kumtornkittikul, H. Hara, T. Yamashita, J. Tanabe, M. Uchiyama, Y. Tsuboi, T. Miyamori, T. Kitahara, H. Sato, Y. Homma, S. Matsumoto, K. Seki, Y. Watanabe, M. Hamada, and M. Takahashi. ISSCC, page 262-263. IEEE, (2008)

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Toko Fujita

Tetsuya Takahashi

Buntaro Fujita

Masayuki Fujita

Tetsuya Mizutani

Other publications of authors with the same name

A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm.Y. Kikuchi, M. Takahashi, T. Maeda, H. Hara, H. Arakida, H. Yamamoto, Y. Hagiwara, T. Fujita, M. Watanabe, T. Shimazawa and 4 other author(s). ISSCC, page 326-327. IEEE, (2010)A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme.T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako and 3 other author(s). IEEE J. Solid State Circuits, 31 (11): 1770-1779 (1996)A single-chip 802.11a MAC/PHY with a 32-b RISC processor.T. Fujisawa, J. Hasegawa, K. Tsuchie, T. Shiozawa, T. Fujita, T. Saito, and Y. Unekawa. IEEE J. Solid State Circuits, 38 (11): 2001-2009 (2003)Improvement of Factor Model with Text Information Based on Factor Model Construction Process.R. Saga, T. Fujita, K. Kitami, and K. Matsumoto. IIMSS, volume 254 of Frontiers in Artificial Intelligence and Applications, page 222-230. IOS Press, (2013)A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme.M. Takahashi, M. Hamada, T. Nishikawa, H. Arakida, T. Fujita, F. Hatori, S. Mita, K. Suzuki, A. Chiba, T. Terazawa and 8 other author(s). IEEE J. Solid State Circuits, 33 (11): 1772-1780 (1998)MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing.R. Jr., and T. Fujita. ISCA, page 443-451. IEEE Computer Society, (1988)Learning of situation dependent prediction toward acquiring physical causality.M. Ogino, T. Fujita, S. Fuke, and M. Asada. EpiRob, (2009)Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems.C. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, and Y. Oowaki. IEEE Trans. Very Large Scale Integr. Syst., 14 (12): 1379-1383 (2006)A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS.C. Teh, T. Fujita, H. Hara, and M. Hamada. ISSCC, page 338-340. IEEE, (2011)A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI.M. Hamada, H. Hara, T. Fujita, C. Teh, T. Shimazawa, N. Kawabe, T. Kitahara, Y. Kikuchi, T. Nishikawa, M. Takahashi and 1 other author(s). CICC, page 527-530. IEEE, (2005)

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