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Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training.

, , , , , and . ICML, volume 162 of Proceedings of Machine Learning Research, page 19123-19138. PMLR, (2022)

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AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies., , , , , , , , , and . ISPD, page 175-183. ACM, (2022)Resilient Design Techniques for Improving Cache Energy Efficiency.. University of California, Berkeley, USA, (2015)Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM., , , , , and . ESSDERC, page 98-101. IEEE, (2014)Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture., , , , , , , , , and 7 other author(s). MICRO, page 14-27. ACM, (2019)A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2019)A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 52 (7): 1863-1875 (2017)An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process., , , , , and . VLSI Technology and Circuits, page 146-147. IEEE, (2022)A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 154-155. IEEE, (2022)Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training., , , , , and . ICML, volume 162 of Proceedings of Machine Learning Research, page 19123-19138. PMLR, (2022)On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC., , , , , , , , and . A-SSCC, page 125-128. IEEE, (2016)