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Disambiguation of "Pellizzoni, Rodolfo"

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SCE-Comm: A Real-Time Inter-Core Communication Framework for Strictly Partitioned Multi-core Processors.

, , , , , , and . MECO, page 1-6. IEEE, (2020)

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Rodolfo Stecher

Rodolfo Mazzi

Rodolfo Ferrini

Rodolfo Valentino

Rodolfo Deppe

 

Other publications of authors with the same name

A composable worst case latency analysis for multi-rank DRAM devices under open row policy., , and . Real Time Syst., 52 (6): 761-807 (2016)A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources., , , , and . ECRTS, volume 262 of LIPIcs, page 17:1-17:25. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2023)A Requests Bundling DRAM Controller for Mixed-Criticality Systems., and . RTAS, page 247-258. IEEE Computer Society, (2017)Memory Servers for Multicore Systems., and . RTAS, page 97-108. IEEE Computer Society, (2016)HopliteBuf: FPGA NoCs with Provably Stall-Free FIFOs., , , and . FPGA, page 222-231. ACM, (2019)A design-space exploration for allocating security tasks in multicore real-time systems., , , and . DATE, page 225-230. IEEE, (2018)ASIIST: Application Specific I/O Integration Support Tool for Real-Time Bus Architecture Designs., , , and . ICECCS, page 11-22. IEEE Computer Society, (2009)Toward the Predictable Integration of Real-Time COTS Based Systems., and . RTSS, page 73-82. IEEE Computer Society, (2007)A Slot-Based Real-Time Scheduling Algorithm for Concurrent Transactions in NoC., , and . RTCSA (1), page 329-338. IEEE Computer Society, (2011)Real-Time I/O Management System with COTS Peripherals., , , , and . IEEE Trans. Computers, 62 (1): 45-58 (2013)