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Physical design of supergate cells aiming geometrical optimizations., , , , , и . MWSCAS, стр. 1-4. IEEE, (2016)Transistor placement strategies for non-series-parallel cells., , , , , и . MWSCAS, стр. 523-526. IEEE, (2017)A New Technique Using Tunnel Shape Information to Improve Path Search in Detailed Routing., , и . NEWCAS, стр. 243-247. IEEE, (2018)Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding., , , , и . MWSCAS, стр. 1-4. IEEE, (2016)An Improved Heuristic Function for A∗-Based Path Search in Detailed Routing., , и . ISCAS, стр. 1-5. IEEE, (2019)A Fast Approximate Function Generation Method to ATMR Architecture., , , и . LASCAS, стр. 1-4. IEEE, (2022)Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization., , , , , , , , , и 31 other автор(ы). DATE, стр. 1026-1031. IEEE, (2021)Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design., , , , и . LASCAS, стр. 1-4. IEEE, (2022)Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients., , и . ITC, стр. 1-9. IEEE, (2020)An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults., , , и . VLSI-SoC (Selected Papers), том 586 из IFIP Advances in Information and Communication Technology, стр. 69-88. Springer, (2019)