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Disambiguation of "Nath, Siddhartha"

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The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap.

, , , and . ICCD, page 153-160. IEEE Computer Society, (2014)

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Siddhartha Chattopadhyay

Siddhartha Roy

Siddhartha Kargupta

Siddhartha Schwenzer

Siddhartha Chib

 

Other publications of authors with the same name

Generative self-supervised learning for gate sizing: invited., , , , , and . DAC, page 1331-1334. ACM, (2022)Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes., and . ISPD, page 83-90. ACM, (2021)BufFormer: A Generative ML Framework for Scalable Buffering., , , , and . ASP-DAC, page 264-270. ACM, (2023)A deep learning methodology to proliferate golden signoff timing., , , and . DATE, page 1-6. European Design and Automation Association, (2014)Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper., , , , , , , and . ICCAD, page 1-6. IEEE, (2021)Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper)., , , , and . ICCAD, page 1:1-1:8. ACM, (2022)Learning-based prediction of embedded memory timing failures during initial floorplan design., , , , and . ASP-DAC, page 178-185. IEEE, (2016)BEOL stack-aware routability prediction from placement using data mining techniques., , , , and . ICCD, page 41-48. IEEE Computer Society, (2016)SI for free: machine learning of interconnect coupling delay and transition effects., , and . SLIP, page 1-8. IEEE Computer Society, (2015)Learning-based approximation of interconnect delay and slew in signoff timing tools., , , , and . SLIP, page 1-8. IEEE Computer Society, (2013)