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System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents.

, , , , and . IRPS, page 1-7. IEEE, (2022)

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Methodology for extracting the characteristic capacitances of a power MOSFET transistor, using conventional on-wafer testing techniques., , , and . ESSDERC, page 221-225. IEEE, (2012)Method to assess the impact of LER and spacing variation on BEOL dielectric reliability using 2D-field simulations for <20nm spacing., , , , , and . IRPS, page 10-1. IEEE, (2018)Exploring the Reliability Limits for the Z-Pitch Scaling of Molybdenum Inter-Word Line Oxides in 3D NAND., , , , , , , , , and . IRPS, page 1-5. IEEE, (2024)A pragmatic network-aware paradigm for system-level electromigration predictions at scale., , , and . IRPS, page 1-6. IEEE, (2023)A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network., , , , and . SLIP, page 1-7. IEEE, (2021)De-Coupling Thermo-Migration from Electromigration Using a Dedicated Test Structure., , , , , , , , and . IRPS, page 1-5. IEEE, (2024)Challenges for Interconnect Reliability: From Element to System Level., , , , and . ISPD, page 106. ACM, (2023)Metodi e strumentazione per la caratterizzazione di interconnessioni VLSI.. University of Pisa, Italy, (2001)Impact of process variability on BEOL TDDB lifetime model assessment., , , , and . IRPS, page 5. IEEE, (2015)Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies., , , , , , , , , and 6 other author(s). ESSDERC, page 102-105. IEEE, (2014)