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Disambiguation of "Ge, Fen"

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Optimization of Area and Delay for Implementation of the Composite Field Advanced Encryption Standard S-Box.

, , , and . J. Circuits Syst. Comput., 25 (5): 1650037:1-1650037:29 (2016)

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Fen Wang

Fen Guo

Fen Zhou

Junbo Ge

Wancheng Ge

 

Other publications of authors with the same name

A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture., , and . ASICON, page 1-5. IEEE, (2023)A network components insertion method for 3D application-specific Network-on-Chip., , , and . ASICON, page 1-4. IEEE, (2015)Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (10): 3041-3054 (2016)Distributed Synchronization for Message-Passing Based Embedded Multiprocessors., , , , and . IEICE Trans. Inf. Syst., 98-D (2): 272-275 (2015)Exploring memory controller configurations for many-core systems with 3D stacked DRAMs., , , and . ISQED, page 565-570. IEEE, (2015)Implementation of Bidirectional LSTM Accelerator Based on FPGA., , , and . ICCT, page 1512-1516. IEEE, (2022)A Vehicle Line-Pressing Detection Approach Based on YOLOv5 and DeepSort., , and . ICCT, page 1745-1749. IEEE, (2022)A thermal-aware mapping algorithm for 3D Mesh Network-on-Chip architecture., , , and . ASICON, page 1-4. IEEE, (2013)FPGA implementation and verification of efficient and reconfigurable CNN-LSTM accelerator design., , and . AIBDF, page 245-250. ACM, (2023)A two-phase floorplanning approach for Application-specific Network-on-Chip., , , and . ASICON, page 1-4. IEEE, (2013)