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VMIN Characterization Circuits in 10nm CMOS.

A. Agarwal, S. Hsu, S. Realov, M. Anders, G. Chen, M. Kar, R. Kumar, H. Sumbul, P. Knag, H. Kaul, S. Mathew, M. Kumashikar, R. Krishnamurthy, and V. De. ISSCC, page 392-394. IEEE, (2020)

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Himanshu Raj

Himanshu Verma

Himanshu Tyagi

Himanshu Ghildiyal

Himanshu Patel

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18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS.R. Ramanarayanan, S. Mathew, F. Sheikh, S. Srinivasan, A. Agarwal, S. Hsu, H. Kaul, M. Anders, V. Erraguntla, and R. Krishnamurthy. ESSCIRC, page 210-213. IEEE, (2010)Near-threshold voltage (NTV) design: opportunities and challenges.H. Kaul, M. Anders, S. Hsu, A. Agarwal, R. Krishnamurthy, and S. Borkar. DAC, page 1153-1158. ACM, (2012)A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS.A. Agarwal, S. Hsu, S. Mathew, M. Anders, H. Kaul, F. Sheikh, and R. Krishnamurthy. ESSCIRC, page 177-180. IEEE, (2012)Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS.S. Hsu, A. Agarwal, S. Realov, M. Anders, G. Chen, M. Kar, R. Kumar, H. Sumbul, P. Knag, H. Kaul and 6 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS.S. Hsu, A. Agarwal, M. Anders, H. Kaul, S. Mathew, F. Sheikh, R. Krishnamurthy, and S. Borkar. VLSIC, page 118-119. IEEE, (2012)A 350mV-900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS.A. Agarwal, S. Hsu, M. Anders, S. Mathew, G. Chen, H. Kaul, S. Satpathy, and R. Krishnamurthy. VLSI Circuits, page 1-2. IEEE, (2016)A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS.M. Anders, H. Kaul, M. Hansson, R. Krishnamurthy, and S. Borkar. ESSCIRC, page 182-185. IEEE, (2008)Clock net optimization using active shielding.H. Kaul, D. Sylvester, and D. Blaauw. ESSCIRC, page 265-268. IEEE, (2003)A novel buffer circuit for energy efficient signaling in dual-VDD systems.H. Kaul, and D. Sylvester. ACM Great Lakes Symposium on VLSI, page 462-467. ACM, (2005)DVS for On-Chip Bus Designs Based on Timing Error Correction.H. Kaul, D. Sylvester, D. Blaauw, T. Mudge, and T. Austin. DATE, page 80-85. IEEE Computer Society, (2005)

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Disambiguation of "Kaul, Himanshu"

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25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS.

Please choose a person to relate this publication to

Himanshu Raj

Himanshu Verma

Himanshu Tyagi

Himanshu Ghildiyal

Himanshu Patel

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Kaul, Himanshu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS.

Please choose a person to relate this publication to

Himanshu Raj

Himanshu Verma

Himanshu Tyagi

Himanshu Ghildiyal

Himanshu Patel

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS.