( en | de | ru )

 

Disambiguation of "Sumbul, Huseyin"

Author of the publication

copydeleteadd this publication to your clipboard
25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS.

, , , , , , , , , , , , , and . ISSCC, page 392-394. IEEE, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Oral Sümbül

Hüseyin Diril

Hüseyin Okur

Hüseyin Oguz

Hüseyin Kurt

 

Other publications of authors with the same name

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 392-394. IEEE, (2020)Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs., , , , , , , , , and 6 other author(s). FCCM, page 199-207. IEEE, (2019)A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications., , , , , , , , , and 4 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS., , , , , , , , , and 6 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI., , , , , , , , , and 6 other author(s). FPGA, page 119. ACM, (2019)System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars., , , , , , , , , and 2 other author(s). CICC, page 1-8. IEEE, (2022)Building trusted ICs using split fabrication., , , , and . HOST, page 1-6. IEEE Computer Society, (2014)Efficient and secure intellectual property (IP) design with split fabrication., , , , , and . HOST, page 13-18. IEEE Computer Society, (2014)A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS., , , , and . VLSI Circuits, page 255-256. IEEE, (2018)A Novel Design Methodology for Synthesizing Application-Specific Logic-in-Memory Blocks.. Carnegie Mellon University, USA, (2015)