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Disambiguation of "Geuskens, Bibiche M."

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A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance.

, , , , , , , , , , and . ISSCC, page 282-283. IEEE, (2010)

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Simon M M Laimer

M. Biswas M. Dam

Marcel M M Kuypers

Bernhard M M Lang

Doris M M Eggert

 

Other publications of authors with the same name

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops., , , , , , , , , and 1 other author(s). IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (3): 208-217 (2011)A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 46 (1): 194-208 (2011)PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction., , , , , , , , and . ISSCC, page 352-353. IEEE, (2010)16.1 A nanogap transducer array on 32nm CMOS for electrochemical DNA sequencing., , , , , , , , , and 1 other author(s). ISSCC, page 288-289. IEEE, (2016)Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency., , , , , , , , , and . CICC, page 1-4. IEEE, (2010)Resilient microprocessor design for high performance & energy efficiency., , , , , , , , , and 1 other author(s). ISLPED, page 355-356. ACM, (2010)Resilient design in scaled CMOS for energy efficiency., , , , , , , , , and 2 other author(s). ASP-DAC, page 625. IEEE, (2010)A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance., , , , , , , , , and 1 other author(s). ISSCC, page 282-283. IEEE, (2010)Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM., , , , , and . ISSCC, page 234-236. IEEE, (2012)Content Addressable Memory for Low-Power and High-Performance Applications., , and . CSIE (3), page 423-427. IEEE Computer Society, (2009)