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Disambiguation of "Khellah, Muhammad M."

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A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance.

, , , , , , , , , , and . ISSCC, page 282-283. IEEE, (2010)

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Muhammad Muhammad

Muhammad Al Muhammad

Muhammad Muhammad Sulaim n

Muhammad Sir ju-'l-Isl m

Muhammad Nazir

 

Other publications of authors with the same name

Advances in Microprocessor Cache Architectures Over the Last 25 Years., , , , , , , , and . IEEE Micro, 41 (6): 78-88 (2021)A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique., , , , and . IEEE J. Solid State Circuits, 38 (5): 839-842 (2003)Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches., , , and . ISCAS, IEEE, (2006)Reducing the Data Switching Activity on Serial Link Buses., , , and . ISQED, page 425-432. IEEE Computer Society, (2006)A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors., , , , , , , and . ICCD, page 253-257. IEEE Computer Society, (2005)A fully integrated charge sharing active decap scheme for power supply noise suppression., , , , , and . SoCC, page 374-379. IEEE, (2015)2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process., , , , , , , , , and 1 other author(s). ISSCC, page 274-275. IEEE, (2008)8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation., , , , , , , , , and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating., , , , , , , , and . IEEE J. Solid State Circuits, 52 (1): 50-63 (2017)A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 46 (1): 194-208 (2011)