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Case Study: Efficient SDD test generation for very large integrated circuits., , , , и . VTS, стр. 78-83. IEEE Computer Society, (2011)TSUNAMI: a light-weight on-chip structure for measuring timing uncertainty induced by noise during functional and test operations., и . ACM Great Lakes Symposium on VLSI, стр. 183-188. ACM, (2012)A new hybrid FPGA with nanoscale clusters and CMOS routing., и . DAC, стр. 727-730. ACM, (2006)Trustworthy Hardware: Identifying and Classifying Hardware Trojans., , , и . Computer, 43 (10): 39-46 (2010)Enhanced launch-off-capture transition fault testing., , и . ITC, стр. 10. IEEE Computer Society, (2005)Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes., , , , , , , , , и . DDECS, стр. 376-381. IEEE Computer Society, (2010)Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation., , , и . DATE, стр. 1172-1177. ACM, (2008)Critical Paths Selection and Test Cost Reduction Considering Process Variations., и . Asian Test Symposium, стр. 259-264. IEEE Computer Society, (2013)Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure.. DFT, стр. 305-313. IEEE Computer Society, (2005)Securing Scan Design Using Lock and Key Technique., , , и . DFT, стр. 51-62. IEEE Computer Society, (2005)