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A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification.

, , , and . DAC, page 1-6. IEEE, (2020)

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An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural Networks., , and . DATE, page 575-580. IEEE, (2021)A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification., , , , and . CoRR, (2020)A 40-nm 1.89-pJ/SOP Scalable Convolutional Spiking Neural Network Learning Core With On-Chip Spatiotemporal Back-Propagation., and . IEEE Trans. Very Large Scale Integr. Syst., 31 (12): 1994-2007 (December 2023)A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array., , , , and . VLSI-DAT, page 1-4. IEEE, (2022)A Low-Bitwidth Integer-STBP Algorithm for Efficient Training and Inference of Spiking Neural Networks., and . ASP-DAC, page 651-656. ACM, (2023)Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method., , , , , and . ITC, page 601-608. IEEE, (2022)A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification., , , and . DAC, page 1-6. IEEE, (2020)A Decision Tree-Based Screening Method for Improving Test Quality of Memory Chips., , , , , and . ITC-Asia, page 19-24. IEEE, (2022)Weak Die Screening by Feature Prioritized Random Forest for Improving Semiconductor Quality and Reliability., , , , , and . ITC-Asia, page 25-30. IEEE, (2022)