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A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification.

, , , and . DAC, page 1-6. IEEE, (2020)

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General Modular Multiplication by Block Multiplication and Table Lookup., and . ISCAS, page 295-298. IEEE, (1994)Processor-programmable memory BIST for bus-connected embedded memories., and . ASP-DAC, page 325-330. ACM, (2001)An adaptive code rate EDAC scheme for random access memory., and . DATE, page 735-740. IEEE Computer Society, (2010)Low-Cost Modular Totally Self-Checking Checker Design for m-out-of-n Code., and . IEEE Trans. Computers, 48 (8): 815-826 (1999)Sequential circuit fault simulation using logic emulation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (8): 724-736 (1998)DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (9): 1356-1369 (2014)Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (11): 1328-1336 (2002)Built-In Self-Repair Schemes for Flash Memories., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (8): 1243-1256 (2010)Testing and Diagnosis Methodologies for Embedded Content Addressable Memories., , and . J. Electron. Test., 19 (2): 207-215 (2003)TSC Berger-Code Checker Design for 2r-1-Bit Information., and . J. Inf. Sci. Eng., 15 (3): 429-440 (1999)