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A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification.

, , , и . DAC, стр. 1-6. IEEE, (2020)

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Ming-Kuei Lu

Lu Lu

Helmar Minger

Bernhard Mingers

Roland Minges

 

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Design space exploration with a cycle-accurate systemC/TLM DRAM controller model., , , , , , и . VLSI-DAT, стр. 1-4. IEEE, (2017)Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks., , , , , , и . AICAS, стр. 1-4. IEEE, (2021)A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification., , , и . DAC, стр. 1-6. IEEE, (2020)Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications., , , , , , и . SoCC, стр. 286-291. IEEE, (2014)A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification., , , , и . CoRR, (2020)NNSim: A Fast and Accurate SystemC/TLM Simulator for Deep Convolutional Neural Network Accelerators., , , , и . VLSI-DAT, стр. 1-4. IEEE, (2019)Reconfigurable Network-on-chip design for heterogeneous multi-core system architecture., , и . HPCS, стр. 523-526. IEEE, (2014)HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration., , , , и . SOCC, стр. 1-6. IEEE, (2023)MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy., , , , и . ICCD, стр. 614-622. IEEE, (2023)Efficient Segment-wise Pruning for DCNN Inference Accelerators., , , , , , и . VLSI-DAT, стр. 1-4. IEEE, (2022)