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Optimized Distribution of an Accelerated Convolutional Neural Network across Multiple FPGAs.

, , , , , and . FCCM, page 235. IEEE, (2020)

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Scalable Load and Store Processing in Latency-Tolerant Processors., , , , and . IEEE Micro, 26 (1): 30-39 (2006)Virtual Register Renaming., , and . ARCS, volume 7767 of Lecture Notes in Computer Science, page 86-97. Springer, (2013)Optimized Distribution of an Accelerated Convolutional Neural Network across Multiple FPGAs., , , , , and . FCCM, page 235. IEEE, (2020)Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors., , and . MICRO, page 423-. IEEE Computer Society, (2003)A Mediation Layer for Connecting Data-Intensive Applications to Reconfigurable Data Nodes., , , , , , , , , and . ICCCN, page 1-9. IEEE, (2013)Minimalist Design for Accelerating Convolutional Neural Networks for Low-End FPGA Platforms., , , , , , and . FCCM, page 196. IEEE Computer Society, (2017)Tuning the continual flow pipeline architecture., and . ICS, page 243-252. ACM, (2013)Recycling waste: exploiting wrong-path execution to improve branch prediction., , and . ICS, page 12-21. ACM, (2003)X86-ARM binary hardware interpreter., , and . ICECS, page 145-148. IEEE, (2011)Issues in Trustworthy Software Systems., and . TrustCom/BigDataSE/ISPA (1), page 1142-1147. IEEE, (2015)