( en | de | ru )

 

Disambiguation of "Rajwar, Ravi"

Author of the publication

copydeleteadd this publication to your clipboard
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors.

, , and . MICRO, page 423-. IEEE Computer Society, (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ravi Walli

Mylapore Ravi

Holger Raviol

Jewgeni Ravik

Samatha Ravipati

 

Other publications of authors with the same name

An Architectural Evaluation of Java TPC-W., , , and . HPCA, page 229-240. IEEE Computer Society, (2001)Transactional Memory, 2nd Edition, , and . Synthesis Lectures on Computer Architecture Morgan & Claypool Publishers, (2010)Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance., , , , and . IEEE Micro, 24 (6): 62-73 (2004)Transactional memory and the birthday paradox., and . SPAA, page 303-304. ACM, (2007)Improving the Throughput of Synchronization by Insertion of Delays., , and . HPCA, page 168-179. IEEE Computer Society, (2000)Towards an Adaptable Systems Architecture for Memory Tiering at Warehouse-Scale., , , , , , , , , and 8 other author(s). ASPLOS (3), page 727-741. ACM, (2023)Performance evaluation of Intel® transactional synchronization extensions for high-performance computing., , , and . SC, page 19:1-19:11. ACM, (2013)Inferential queueing and speculative push for reducing critical communication latencies., , and . ICS, page 273-284. ACM, (2003)Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors., , and . MICRO, page 423-. IEEE Computer Society, (2003)Scalable Load and Store Processing in Latency-Tolerant Processors., , , , and . IEEE Micro, 26 (1): 30-39 (2006)