( en | de | ru )

 

Disambiguation of "Tarawneh, Ghaith"

Author of the publication

copydeleteadd this publication to your clipboard
Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial Tools.

, and . ASYNC, page 43-50. IEEE Computer Society, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Monther Tarawneh

Mohamed Fayez Tarawneh

Mohamed Fayez Tarawneh

Hussein al- Tarawneh

Mohamed Fayez Tarawneh

 

Other publications of authors with the same name

Significance-Driven Logic Compression for Energy-Efficient Multiplier Design., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 417-430 (2018)Approximate adder segmentation technique and significance-driven error correction., , , , and . PATMOS, page 1-6. IEEE, (2017)Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial Tools., and . ASYNC, page 43-50. IEEE Computer Society, (2018)Intra-chip physical parameter sensor for FPGAS using flip-flop metastability., , and . FPL, page 373-379. IEEE, (2012)An RTL method for hiding clock domain crossing latency., and . ICECS, page 540-543. IEEE, (2012)Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip., , , , and . PDP, page 384-391. IEEE Computer Society, (2014)Collaborative Content Creation: Impact of Media Type on Author Behavior., , , and . CSCW Companion, page 341-344. ACM, (2018)Adaptive Synchronization for DVFS Applications., and . PATMOS, volume 7606 of Lecture Notes in Computer Science, page 93-102. Springer, (2012)Energy-efficient approximate multiplier design using bit significance-driven logic compression., , , , and . DATE, page 7-12. IEEE, (2017)An FPGA-based hardware accelerator for simulating spatiotemporal neurons., and . ICECS, page 618-621. IEEE, (2014)