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Disambiguation of "Cochet, Martin"

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Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC.

, , , , , , , , , , , , , and . ESSCIRC, page 269-272. IEEE, (2016)

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Ay Cochet

Olivier Cochet

Martin Breitenfeldt

Mass measurements on short-lived Cd and Ag nuclides at the online mass spectrometer ISOLTRAP. Uni Greifswald, (2009)

Martin Faes

Analyse der mehrskaligen Transportmechanismen beim laminaren Mischen mittels laseroptischer und numerischer Methoden. Uni Hannover, (2009)

Martin Klug

The late Quaternary environmental and climatic history of North-East Greenland, inferred from coastal lakes. Uni Köln, (2009)
 

Other publications of authors with the same name

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration., , , , , , , , , and 19 other author(s). ISSCC, page 262-264. IEEE, (2024)A 400-ns-Settling- Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology., , , , , , , , , and 8 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2024)On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC., , , , , , , , and . A-SSCC, page 125-128. IEEE, (2016)A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC., , , , , , , , , and 8 other author(s). ESSCIRC, page 269-272. IEEE, (2022)Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC., , , , , , , , , and 4 other author(s). ESSCIRC, page 269-272. IEEE, (2016)A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components., , , , , , , , , and 8 other author(s). ICCAD, page 20:1-20:9. ACM, (2022)A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI., , , , , and . ESSCIRC, page 153-162. IEEE, (2017)Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration., , , , , , , , , and 1 other author(s). CICC, page 1-8. IEEE, (2024)BlitzCoin: Fully Decentralized Hardware Power Management for Accelerator-Rich SoCs., , , , , , , , , and 3 other author(s). ISCA, page 801-817. IEEE, (2024)