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Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs.

, , , , , , , , , , и . CoRR, (2018)

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A Comparison of the AES Candidates Amenability to FPGA Implementation., и . AES Candidate Conference, стр. 28-39. National Institute of Standards and Technology,, (2000)SPADES: A Productive Design Flow for Versal Programmable Logic., , , и . FPL, стр. 65-71. IEEE, (2023)OLAF'17: Third International Workshop on Overlay Architectures for FPGAs., и . FPGA, стр. 1. ACM, (2017)Should the academic community launch an open-source FPGA device and tools effort?: evening panel.. FPGA, стр. 3-4. ACM, (2011)Instruction-Level Parallelism for Reconfigurable Computing., и . FPL, том 1482 из Lecture Notes in Computer Science, стр. 248-257. Springer, (1998)Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs., , , , , , , , , и 1 other автор(ы). CoRR, (2018)The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks., и . FCCM, стр. 303-. IEEE Computer Society, (2002)Reconfigurable computing in the era of post-silicon scaling panel discussion., , , , , , и . FCCM, IEEE Computer Society, (2013)Datapath-oriented FPGA mapping and placement for configurable computing., и . FCCM, стр. 234-235. IEEE Computer Society, (1997)Synthesis of LUT Networks for Random-Looking Dense Functions with Don't Cares - Towards Efficient FPGA Implementation of DNN., , , и . FCCM, стр. 126-132. IEEE, (2024)