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Disambiguation of "Onodera, Hidetoshi"

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A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation.

, , , , , , and . A-SSCC, page 69-72. IEEE, (2018)

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Kaoru Onodera

Keiichi Onodera

Hidetoshi Yamabe

 

Other publications of authors with the same name

ST: PERL package for simulation and test environment., and . ISCAS (5), page 89-92. IEEE, (2001)Statistical modeling of gate-delay variation with consideration of intra-gate variability., , and . ISCAS (5), page 513-516. IEEE, (2003)Perturbation-immune radiation-hardened PLL with a switchable DMR structure., , and . IOLTS, page 128-132. IEEE, (2013)A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing., , , , , and . ISVLSI, page 488-493. IEEE, (2020)Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS., , , , , , and . IEICE Trans. Electron., 103-C (10): 489-496 (2020)Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs., and . IEEE Trans. Very Large Scale Integr. Syst., 22 (12): 2535-2548 (2014)2016 ASP-DAC.. IEEE Des. Test, 33 (3): 133-134 (2016)A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (12): 2776-2784 (2017)Statistical Gate Delay Model for Multiple Input Switching., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (12): 3070-3078 (2009)On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator., and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (3): 183-187 (2014)