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Disambiguation of "Güntzel, José Luís Almada"

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Rate-constrained successive elimination of Hadamard-based SATDs.

, , , and . ICIP, page 2395-2399. IEEE, (2016)

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José Luis Morote

José Luis Rivarola

José Luis Narro

Luis José Garcés

José Luis Goity

 

Other publications of authors with the same name

Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits., , , , , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 501-510. Springer, (2003)Improving Critical Path Identification in Functional Timing Analysis., , , and . SBCCI, page 297-302. IEEE Computer Society, (2003)A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation., , , and . ACM Trans. Design Autom. Electr. Syst., 19 (4): 40:1-40:25 (2014)Physical design methodologies for performance predictability and manufacturability., , and . Conf. Computing Frontiers, page 390-397. ACM, (2004)Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing Optimization., , , , and . ICCAD, page 528-535. IEEE, (2015)Energy-efficient multi-task computing on MPSoCs: A case study from a memory perspective., , and . ICECS, page 905-908. IEEE, (2012)A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency., , , and . ISVLSI, page 127-132. IEEE Computer Society, (2010)A Transistor Sizing Method Applied to an Automatic Layout Generation Tool., , , , and . SBCCI, page 303-. IEEE Computer Society, (2003)An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms., , , and . SBCCI, page 149-154. ACM, (2011)Rate-constrained successive elimination of Hadamard-based SATDs., , , and . ICIP, page 2395-2399. IEEE, (2016)