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Disambiguation of "Martos, David Guerrero"

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Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits.

, , , , , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 501-510. Springer, (2003)

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Andreas Martos

Lilián Guerrero

Pablo Guerrero

Mariano Guerrero

Sonia Guerrero

 

Other publications of authors with the same name

Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates., , , , , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 389-398. Springer, (2008)Using the complement of the cosine to compute trigonometric functions., , , , , , and . EURASIP J. Adv. Signal Process., 2020 (1): 1-21 (2020)Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements., , , , , , and . IES, page 1-7. IEEE, (2006)Improving the Performance of Static CMOS Gates by Using Independent Bodies., , , , , , and . J. Low Power Electron., 3 (1): 70-77 (2007)Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level., , , , and . PATMOS, volume 2451 of Lecture Notes in Computer Science, page 400-408. Springer, (2002)Static Power Consumption in CMOS Gates Using Independent Bodies., , , , , , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 404-412. Springer, (2007)Signal Sampling Based Transition Modeling for Digital Gates Characterization., , , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 829-837. Springer, (2004)Internode: Internal Node Logic Computational Model., , , , , and . Annual Simulation Symposium, page 241-248. IEEE Computer Society, (2003)Design of a FFT/IFFT module as an IP core suitable for embedded systems., , , , , , , and . SIES, page 337-340. IEEE, (2007)Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits., , , , , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 501-510. Springer, (2003)